As the frequencies of modem computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock signal is often transmitted to help recover the data. The clock signal determines when the data signal should be sampled by a receiver's circuits.
The transmitted clock signal may transition at the beginning of the time the data is valid; however, the receiver's circuits should latch the data during the middle of the time the data is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1 shows a block diagram of a typical communication system (10). The communication system (10) includes multiple links. Each link may include multiple data lines and an associated clock line. Data lines (14) that are N bits wide connect between circuit A (12) and circuit B (34). To aid in the recovery of transmitted data on the data lines (14), a clock signal on clock A line (16) is transmitted with data signals on the data lines (14). Another link includes data lines (24) that are M bits wide and a clock Z line (26). A clock signal on the clock Z line (26) is transmitted with data signals on the data lines (24) to determine when the data signals on the data lines (24) should be latched.
Data signals on the data lines (14, 24) are transmitted from circuit A (12) to circuit B (34). Circuit A (12) and circuit B (34) could also have one or more links to transmit data from circuit B (34) to circuit A (12) along with one or more additional clock signals (not shown). Alternatively, the links between circuit A (12) and circuit B (34) could be bi-directional. The decision as to which circuit may transmit at any given time is defined by a protocol.
The data signals and clock signals transmit information from circuit A (12) to circuit B (34) under the direction of control signals. The control signals are transmitted between circuit A (12) and circuit B (34) on control lines (32) that are K bits wide. The control signals may determine on which cycle, what frequency, and/or under which operating mode the data signals and clock signals should be transmitted. The control signals may request that circuit A (12) transmit a predetermined test pattern to circuit B (34) to test and improve transmission across the link.
In FIG. 2, a block diagram of a typical receiver (200) is shown. A clock signal (201) is input to a DLL (252) so that the DLL (252) generates a phased output, clk_out signal (213). The clock signal (201) is used as an input to a voltage-controlled delay line (210) and to a phase detector (202). The phase detector (202) measures whether the phase difference between the clock signal (201) and clk_out signal (213) of the delay path is correct. An adjustment in the phase delay produces signals that control a charge pump (204). The phase detector (202) indicates that the charge pump (204) should increase or decrease its output using charge pump control signals up, U (203), and down, D (205). The charge pump (204) adds or removes charge from a capacitor C1 (206), that changes a DC value at the input of a bias-generator (208). The capacitor, C1 (206), is connected between a power supply, VDD, and a control voltage, VCTRL (207). The bias-generator (208) produces control voltages, VBP (209) and VBN (211), in response to the control voltage, VCTRL (207), that control the delay of the voltage-controlled delay line (210).
The voltage-controlled delay line (210) may be implemented using current starved elements. This means that the delays are controlled by modifying the amount of current available for charging and discharging capacitances. The linearity of a voltage controlled delay line's characteristics determines the stable range of frequencies over which the DLL can operate. The clk_out signal (213) from the voltage-controlled delay line (210) provides a phase delayed copy of the clock signal (201) to other circuits.
Still referring to FIG. 2, the negative feedback of the clk_out signal (213) adjusts the delay through the voltage-controlled delay line (210) by integrating the phase error that results between the periodic input of the clock signal (201) and clk_out signal (213). The voltage-controlled delay line (210) will delay the clk_out signal (213) by a fixed amount of time such that a desired delay between the clock signal (201) and the clk_out signal (213) is maintained.
The voltage-controlled delay line (210) also has an offset signal (215). The value of the offset signal (215) determines which tap should be used in the voltage-controlled delay line (210) to generate an adjustable clock signal (251). The offset signal (215) may be an analog signal, or a serial or parallel digital signal. While the DLL maintains a fixed delay between the clock signal (201) and the clk_out signal (213), the value of the offset signal (215) adjusts the delay between the clock signal (201) and the adjustable clock signal (251). The adjustable clock signal (251) determines when to latch the incoming data signals on data line 1 (217) through data line V (219) that are Vbits wide.
The adjustable clock signal (251) may be generated from a digital or an analog delay line in place of the voltage-controlled delay line (210). In other embodiments, the adjustable clock signal (251) may be generated from a digital or an analog delay line connected to the clk_out signal (213) outside of the feedback loop. The digital or the analog delay lines in these embodiments may generate the adjustable clock signal (251) based on the value of the offset signal (215). The value of the offset signal (215) is used to determine at which point in the delay line to tap.
The data signals on data line 1 (217) through data line V (219) arrive at flip-flop (212) through flip-flop (214), respectively. The data signals on data line 1 (217) through data line V (219) are latched depending on the arrival time of the adjustable clock (251) to generate latched data signals on chip_data line 1 (221) through chip_data line V (223), respectively. Depending on the arrival time of the adjustable clock signal (251), some or all of the latched data signals may not equal the same state as the data signals.
A pattern comparator (216) is used to test and improve transmission across the link that includes clock signal (201) and data lines (217, 219). A predetermined test pattern signal is transmitted on the data lines (217, 219) under the direction of the control signals (227) that are R bits wide. In some embodiments, the test pattern signal may be transmitted for only one cycle. In other embodiments, the test pattern signal may have a duration that lasts for many cycles on one or more of the data lines (217, 219). As mentioned earlier, the test pattern signal is latched by the flip-flops (212, 214) based on the adjustable clock signal (251). The resulting latched test pattern signals on chip_data line 1 (221) through chip_data line V (223) are compared with the predetermined test pattern signal by the pattern comparator (216).
A test circuit is used to improve the link efficiency. The test circuit includes the pattern comparator (216), an adjustment circuit to adjust the adjustable clock signal (251), and test logic (220). In FIG. 2, the adjustment circuit is part of the voltage-controlled delay line (210). The value of the offset signal (215) selects one of several taps in the delay chain of the voltage-controlled delay line (210) to generate the adjustable clock signal (251). The test logic (220) controls and coordinates the activities of the test sequence.
The test logic (220) selects a value of the offset signal (215) to select a timing of the adjustable clock signal (251) relative to the test pattern signals on data line 1 (217) through data line V (219). The latched test pattern signals on chip_data line 1 (221) through chip_data line V (223) are compared with the test pattern signal by the pattern comparator (216) to determine whether the latched test pattern signals are the same as the test pattern signals. The pattern comparator (216) may send comparison results on signal line (225) to the test logic (220) that indicate a pass or fail, or the number of bits that were not the same.
The test logic (220) may select a different value for the offset signal (215) and repeat the transmission of the test pattern signal, latching the test pattern signal, and comparing the test pattern signal to the latched test pattern signal. The pattern comparator (216) sends the results on signal line (225) to the test logic (220). A set of tests with different selected values for the offset signal (215) may indicate a best selected value or a range of selected values for the offset signal (215). The test logic (220) fixes the selected value for the offset signal (215) to improve transmission across the link. Data signals transmitted across the link under non-test conditions may have a higher probability of successful transmission after the value of the offset signal (215) is appropriately selected.
In FIG. 3, an exemplary timing diagram (300) is shown for one clock cycle of a test pattern signal on one data line (301). Multiple offset values are added to a clock signal to generate multiple adjustable clock signals (303, 305, 307, 309, 311, 313, 315) relative to the one clock cycle of the test pattern signal. The test pattern signal is latched according to a rising edge of the adjustable clock signal (303, 305, 307, 309, 311, 313, or 315). A rising edge of each of the multiple adjustable clock signals (303, 305, 307, 309, 311, 313, 315) is indicated by the vertical lines (321, 323, 325, 327, 329, 331, 333), respectively.
Because the adjustable clock signals (303, 305, 313, 315) may jitter and are temporally located near the beginning or end of the test pattern signal transmission, the latched test pattern signal may not be correct (i.e., a fail). Because the adjustable clock signals (307, 309, 311) are temporally located near the middle of the test pattern signal transmission, the latched test pattern signal may be correct (i.e., a pass). The pass (P) or fail (F) condition is shown as comparison results (317). The pass (P) or fail (F) condition for a link may be based on tests of multiple data lines, multiple cycles of test patterns, and/or repeated test patterns.
The testing of a link is performed during the power-on reset of a central processing unit (CPU) or, more generally, an integrated circuit. Once the value for the offset signal has been determined, it is fixed for the duration of the CPU operation until power is removed or cycled. As the communication system characteristics change due to temperature, voltage, and/or aging effects, the value for the offset signal may not maintain a desired temporal position for the adjustable clock signal to latch the incoming data.